Due to demand for high integration and high capacity semiconductor devices, the design rules have been consistently reduced so as to integrate more semiconductor devices in a semiconductor chip. The power consumption of the semiconductor devices has also increased with the recent tendency for high integration and high capacity of semiconductor devices, so there have been attempts made at reducing power consumption. For example, a DRAM not in the active mode turns off the internal power voltage used in the circuitry and enters the deep power down (DPD) mode to reduce power consumption. In entering/exiting the DPD mode, however, the circuitry is not biased, but may be erroneously triggered because circuit elements may float to unspecified voltage levels.
A conventional technique for preventing the erroneous trigger of circuitry in entering/exiting the DPD mode is disclosed in U.S. Pat. No. 6,560,158. FIG. 1 is a block diagram of an apparatus for controlling an interval voltage in the DPD mode as disclosed in U.S. Pat. No. 6,560,158. Referring to FIG. 1, the DPD voltage control apparatus includes input buffers 110a, 110b and 110c for signaling a DPD entering/exiting signal and providing the signal to a DPD detector and controller 130; the DPD detector and controller 130 for detecting a DPD condition and generating a DPD signal to turn off internal power voltage generators 150a, 150b and 150c in entering the DPD mode and turn on the internal power voltage generators 150a, 150b and 150c in exiting the DPD mode; bias circuitry 160 for biasing a plurality of nodes; an auxiliary input buffer 120 for separately buffering the DPD entering/exiting signal and providing the signal to an automatic pulse generator 170; and the automatic pulse generator 170 for detecting the DPD exiting signal to generate a voltage pulse. This conventional technique reduces the likelihood that the internal circuitry is erroneously triggered by unspecified voltage levels when the internal power voltage generators are turned on/off.
However, the circuitry to which an external power voltage is applied, such as a level shifter for shifting an internal power voltage level to the external power voltage level, is not biased but is floated to a partial voltage level. Particularly, the output of an output circuit is required to be sustained at a high-impedance state in the DPD mode. But the power voltage level of the level shifter is floated to form a current path at the output of the output circuit or to generate output data, which causes power consumption. In circuitry, such as the level shifter to which the external power voltage is applied, the floated power voltage and the external power voltage may cause leakage current and, hence, power consumption. Moreover, unspecified voltage levels may erroneously trigger latches or equipment sensitive to other voltage levels when the internal power voltage generators are turned on/off.